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NXP Semiconductors
PCA24S08
1024 × 8-bit CMOS EEPROM with access protection
5. Pinning information
5.1 Pinning
n.c.
1
8
V DD
n.c.
1
8
V DD
n.c.
PROT
V SS
2
3
4
PCA24S08D
7
6
5
WP
SCL
SDA
n.c.
PROT
V SS
2
3
4
PCA24S08DP
7
6
5
WP
SCL
SDA
002aae845
002aae846
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for TSSOP8
5.2 Pin description
Table 2.
Pin description
Symbol
n.c.
PROT
V SS
SDA
SCL
WP
V DD
Pin
1, 2
3
4
5
6
7
8
Description
not connected
active LOW protect reset input
ground supply voltage
serial data; open-drain I/O
serial clock; open-drain input
active HIGH write protect input
supply voltage
6. Functional description
Refer to Figure 1 “ Block    diagram ” .
6.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA24S08 is shown in Figure 4 .
1
0
1
0
1
B2
B1 R/W
fixed
sofware
selectable
002aae789
Fig 4.
Slave address
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read operation is selected, while logic 0 selects a write operation. Bits B2 and B1
in the slave address represent the 2 most significant bits of the word to be addressed. The
third device address bit in the I 2 C-bus protocol that is usually matched to A2 (pin 3) on a
standard 24C08 serial EEPROM is internally connected HIGH, so device addresses A8h
through AFh (hex) are used to access the memory on the chip.
PCA24S08_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 11 May 2010
? NXP B.V. 2010. All rights reserved.
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